In semiconductor manufacturing chemical mechanical polishing (CMP) is commonly used to planarize dielectric layers between conducting layers. The rate of chemical mechanical polishing (CMP) is dependent upon the relative density of raised areas versus lower areas within a die or within an area of a wafer. An area with a large amount of raised area and a small amount of lower area will polish more slowly than an area with a small amount of raised area and a large amount of lower area.
One type of area with a large amount of raised area and a small amount of lower area is the stepper alignment mark area. In order for the steppers to be able to find the alignment marks, the alignment marks can not be planarized at the chemical mechanical polishing (CMP) step, or if they are, the planarized dielectric must be removed before an opaque film (e.g., polysilicon or metal) is placed on top of the planar dielectric.
In one prior art approach a photoresist mask and etch procedure is performed to remove the dielectric layer from selected structures before the opaque layer is deposited. The alignment marks may be opened during this step. However, because the chemical mechanical polishing (CMP) polish rate is slower, the dielectric thickness over the alignment mark area is thicker than the dielectric thickness over the active circuit components. Therefore, the etch time must be increased. However, increasing a dry etch time can lead to plasma damage or to etching through layers under the dielectric layer. Increasing a wet etch time can lead to undesirable lateral etching and lateral growth of structures or to resist lifting.
In another prior art approach the alignment marks are masked and etched separately. This approach adds cost to the wafer manufacturing process and decreases the overall factory capacity by taxing the lithography equipment (i.e., a factory capacity constraint tool).
In another prior art approach a built in shadow mask is used in the opaque film deposition tool. This approach requires changes to the alignment mark locations. This approach also requires modifications to be made to expensive capital equipment.
Therefore, there is a need in the art for a system and method that is capable of selectively increasing an etch rate in areas that have a large amount of raised area (e.g., alignment marks) without increasing the etch rate in areas that have a small amount of raised area (e.g., the active device regions).